this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.01 / jul.96 hyundai semiconductor HY638256 series 32kx8bit cmos fast sram description the HY638256 is a high-speed 32,768 x 8-bits cmos static ram fabricated using hyundai's high performance twin tub cmos process technology. this high reliability process coupled with high-speed circuit design techniques, yields maximum access time of 15ns. the HY638256 has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0 volt. it is suitable for use in high-density high-speed system applications. features block diagrm m single 5v 10% power supply high speed - 15/20/25ns(max.) low power consumption(max.) mode conditions current units operating 15ns 100 ma 20/25ns 90 ma standby ttl 30 ma cmos 2 ma l 100 ua battery backup(l-part) - 2.0v(min) data retention fully static operation and tri-state outputs - no clock or refresh required ttl compatible inputs and outputs standard pin configuration - 28pin 300mil soj - 28pin 8 x 13.4 mm tsop-i pin connection pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vcc /we a8 a9 a11 /oe a10 /cs1 i/o8 i/o7 i/o6 i/o5 i/o4 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss a13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a10 /cs i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 /oe a11 a9 a8 a13 /we vcc a14 a12 a7 a6 a5 a4 a3 i/o8 soj tsop-i(standard) pin name pin function /cs chip select /we write enable /oe output enable a0~a14 adderss input i/o1~i/o8 data input/output vcc power(+5.0v) vss ground ordering information part no. speed power package HY638256j 15/20/25 soj HY638256lj 15/20/25 l-part soj HY638256t1 15/20/25 tsop-i standard HY638256lt1 15/20/25 l-part tsop-i standard a14 column decoder a0 row decoder memory array 256x1024 sense amp output buffer i/o1 i/o8 add input buffer /cs /oe /we write driver control logic HY638256 series rev.01 / jul.96 3 dc electrical characteristics vcc = 5.0v 10%, t a = 0 c to 70 c , unless otherwise specified. symbol parameter test conditions min type max unit i li input leakage current v ss < v in < v cc -2 - 2 ua i lo output leakage current v ss < v out < v cc , /cs = v ih or / oe = v ih or /we = v il -2 - 2 ua i cc1 average operating /cs = v il , i i/o = 0ma, 15ns - - 100 ma current min. duty cycle = 100% 20/25ns - - 90 ma i sb ttl standby current (ttl inputs) /cs = v ih, v in= v ih or v il, min. cycle - - 30 ma i sb1 cmos standby current /cs > v cc -0.2v, v in > - - 2 ma (cmos inputs) v cc -0.2v or v in < 0.2v l - 20 100 ua v ol output low voltage i ol = 8.0ma - - 0.4 v v oh output high voltage i oh = -4.0ma 2.4 - - v note : typical values are at vcc = 5.0v, t a = 25 c ac characteristics vcc = 5.0v 10%, t a = 0 c to 70 c , unless otherwise specified. -15 -20 -25 min max min max min max 1 trc read cycle time 15 - 20 - 25 - ns 2 taa address access time - 15 - 20 - 25 ns 3 tacs chip select access time - 15 - 20 - 25 ns 4 toe output enable to output valid - 8 - 10 - 12 ns 5 tclz chip select to output in low z 3 - 3 - 3 - ns 6 tolz output enable to output in low z 3 - 3 - 3 - ns 7 tchz chip deselecting to output in high z 0 8 0 10 0 10 ns 8 tohz out disable to output in high z 0 8 0 8 0 8 ns 9 toh output hold from address change 3 - 3 - 3 - ns 10 twc write cycle time 15 - 20 - 25 - ns 11 tcw chip select to end of write 12 - 13 - 15 - ns 12 taw address valid to end of write 12 - 13 - 15 - ns 13 tas address set-up time 0 - 0 - 0 - ns 14 twp write pulse width 12 - 13 - 15 - ns 15 twr write recovery time 0 - 0 - - - ns 16 twhz write to output in high z 0 7 0 9 0 10 ns 17 tdw data to write time overlap 8 - 9 - 10 - ns 18 tdh data hold from write time 0 - 0 - 0 - ns 19 tow output active from end of write 3 - 3 - 3 - ns symbol parameter # read cycle write cycle unit
HY638256 series rev.01 / jul.96 5 timing diagram read cycle 1 addr oe cs data out data valid trc tacs tclz toe tolz taa toh tohz tchz high-z note (read cycle) 1. tchz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, tchz max. is less than tclz min. both for a given device and from device to device. 3. /we is high for read cycle. read cycle 2 trc taa data valid previous data toh toh addr data out note (read cycle) 1. /we is high for read cycle. 2. device is continuously selected /cs=v il . 3. /oe=v il . HY638256 series rev.01 / jul.96 6 write cycle 1(/oe low clocked) addr oe cs data out twc tdw tohz we data valid tdh twp tas data in twr tcw taw write cycle 2(/oe low fixed) tdw twhz we data valid tdh twp tas data in twr tcw taw (7) (8) tow addr cs data out twc
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